The present invention relates to processors, and more specifically, to a method and apparatus for enhancing or improving the performance of the processors. In general, processors may be classified as single core and multiple cores. The multiple cores processors consist of processing logic, termed core, repeated several times on a substrate; while bus and memories are shared among the cores. A typical processor may be regarded as a set of entities consisting of logic to perform specific operations, for example, arithmetic operations, logic operations, and other data processing functions, coupled with mechanism to store data, retrieve data, and instructions from memory.
A measure of performance of a processor is the number of instructions executed per clock cycle. The current trend in processor technology is to increase this number; thereby improving the performance of the processor. Several techniques and features have been added to the architecture of processors to achieve this end. Some examples of features and techniques include cache memories, translation look up blocks (TLB), pipelining, branch prediction logic, etc. One area of concern is the branch prediction logic, which guesses the path through the code that the processor will take. If the guess is correct, the feature does enhance the performance of the processor. However, if the guess or prediction is in error (i.e. wrong), this may reduce the performance of the processor rather than enhance it. The likelihood of under performance by the processor due to erroneous branch prediction is addressed in the embodiment set forth herein.